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introduction the front-end stage of conventional off-line converters, typically made up of a full wave rectifier bridge with a capacitor filter, gets an unregulated dc bus from the ac mains. the filter capacitor must be large enough to have a relatively low ripple superimposed on the dc level. this means that the instantaneous line voltage is below the voltage on the capacitor most of the time, thus the rectifiers conduct only for a small portion of each line half-cycle. the current drawn from the mains is then a series of narrow pulses whose amplitude is 5-10 times higher than the resulting dc value. lots of drawbacks result from that: much higher peak and rms current drawn from the line, distortion of the ac line voltage, overcurrents in the neutral line of the three-phase systems and, after all, a poor utili- sation of the power system's energy capability. this can be measured in terms of either harmonic contents, as norms en61000-3-2 envisage, or power factor (pf), intended as the ratio between the real power (the one transferred to the output) and the ap- parent power (rms line voltage times rms line current) drawn from the mains, which is more immedi- ate. a traditional input stage with capacitive filter has a low pf (0.5-0.7) and high harmonic contents. october 2001 ? AN966 application note l6561, enhanced transition mode power factor corrector by claudio adragna the tm (transition mode) technique is widely used for power factor correction in low power appli- cations, such as lamp ballasts or low-end monitors. the l6561 is the latest st's proposal for this market and the emerging ones that are supposed to require a low-cost power factor correction. based on a well-established architecture, the l6561 offers excellent performance that enlarges its field of application considerably. + - multiplier v ref2 over-voltage detection voltage regulator uvlo internal supply 7v + - 2.5v r1 r2 r s q +- driver starter + - zero current detector disable 2.1v 1.6v v cc 8 1 23 4 zcd v cc inv comp mult cs gd 7 5 gnd 6 d97in547c 20v 40k 5pf figure 1. internal block diagram of the l6561. 1/20
by using switching techniques, a power factor corrector (pfc) preregulator, located between the recti- fier bridge and the filter capacitor, allows to draw from the mains a quasi-sinusoidal current, in-phase with the line voltage. the pf becomes very close to 1 (more than 0.99 is possible) and the aforesaid drawbacks are eliminated. theoretically, any switching topology can be used to achieve a high pf but, in practice, the boost topol- ogy has become the most popular because of the advantages it offers: 1) mainly, the circuit requires the fewest external parts, thus it is the cheapest. additionally: 2) the boost inductor located between the bridge and the switch causes the input di/dt to be low, thus minimizing the noise generated at the input and, therefore, the requirements on the input emi filter; 3) the switch is source-grounded, therefore is easy to drive. however, boost topology requires the dc output voltage to be higher than the maximum expected line peak voltage (400vdc is a typical value for 220v or wide range mains applications). besides, there is no isolation between input and output, thus any line voltage surge will be passed on to the output. two methods of controlling a pfc preregulator are currently widely used: the fixed frequency average current mode pwm and the transition mode (tm) pwm (fixed on-time, variable frequency). the first method needs a complex control that requires a sophisticated controller ic (st's l4981a, with the vari- ant of the frequency modulation offered by the l4981b) and a considerable component count. the sec- ond one requires a simpler control (implemented by st's l6561), much fewer external parts and is therefore much less expensive. with the first method the boost inductor works in continuous conduction mode, while tm makes the in- ductor work on the boundary between continuous and discontinuous mode, by definition. for a given throughput power, tm operation then involves higher peak currents. this, also consistently with cost considerations, suggests its use in a lower power range (typically below 150w), while the former is rec- ommended for higher power levels. l6561 pfc controller integrated circuit the l6561, whose internal block diagram is shown in fig. 1, is an ic intended to control pfc preregula- tors by using the transition mode technique. the device is available in minidip and so8 packages. the most significant features of the l6561 concern the following points: e undervoltage lockout with hysteresis; e true micropower start-up current (50 m a typ., 90 m a guaranteed)for simple start-up circuits (just one re- sistor) with very low power dissipation; e internal reference with 1% precision guaranteed (@ tj=25 c); e disable function to shut down the device and reduce its current consumption; e two-level overvoltage protection; e internal starter and zero current detection circuit for tm operation; e multiplier with extended dynamics for wide range mains applications, with excellent thd; e on-chip rc filter on the current sense pin; e high capability totem pole output for mosfet or igbt drive. the ic is optimised for controlling pfc preregulators based on boost topology in electronic lamp bal- lasts, ac-dc adapters and low power (<150 w) smps. however, its excellent performance along with the extremely reduced external parts count allows also the use in unconventional topologies/applica- tions. low power off-line ac-dc converters (using isolated flyback topology) with or without power fac- tor correction are the most noticeable examples. device blocks description supply block as shown in fig. 1, a linear voltage regulator supplied by vcc generates an internal 7v rail used to supply the whole integrated circuit, except for the output stage which is supplied directly from vcc. in addition, a bandgap circuit generates the precise internal reference (2.5v 1% @ 25 c) used by the control loop to ensure a good regulation. in fig.2 is shown the undervoltage lockout (uvlo) comparator with hysteresis used to enable the chip as long as the vcc voltage is high enough to ensure a reliable operation. AN966 application note 2/20
error amplifier and overvoltage detector block (see fig. 3 and 4): the error amplifier (e/a) inverting input, through an external divider connected to the output bus, com- pares a partition of the boosted output dc voltage, vo, with the internal reference, so to maintain the preregulator output dc voltage constant. the e/a output is used for frequency compensation, usually realised with a feedback capacitor con- nected to the inverting input. the e/a bandwidth will be extremely low because the output of the e/a must be constant over a line half-cycle to achieve high pf. the dynamics of the e/a output is internally clamped so that it can swing between 2v and 5.8v in order to speed up the recovery after the e/a saturates low due to an overvoltage or saturates high because of an overcurrent. the device is provided with a two-level overvoltage protection (ovp), realized by using the pin con- nected to the e/a output. in case of overvoltage, the output of the e/a will tend to saturate low but the e/a response is very slow, so it will take a long time to go into saturation. on the other hand, an overvoltage must be corrected im- mediately. hence a fast ovp detector, based on a different concept, is necessary. in steady state condition, the current through r1 is equal to the current in r2 because the compensation capacitor does not allow dc current to flow (neither does the high-impedance inverting input of the e/a): i r1,r2 = v o - 2.5 r1 = 2.5 r2 when the output voltage rises because of a step load change, the current in r1 builds up as well but the current through r2, fixed by the internal 2.5v reference, does not because of the e/a slowness. the cur- rent in excess will then flow through the feedback capacitor and enter the low-inpedance e/a output, where it is sensed. in case, a two-step procedure can occur. +vi d97in673 ref. uvlo - + 8 figure 2. internal supply block. AN966 application note 3/20
when the current in excess reaches about 37 m a, the output voltage of the multiplier is forced to de- crease thus the energy drawn from the mains is reduced. this slows down the rate of rise of the output voltage. in some cases, this osoft brakingo action is able to prevent the output voltage from exceeding the regulated value too much. if the output voltage further increases despite the soft braking, so that the current entering the e/a reaches 40 m a, a osharp brakingo takes place. the output of the multiplier is pulled to ground, thus turn- ing off the output stage and the external mosfet. also the internal starter is switched off. the internal current comparator is provided with hysteresis, thus the pull-down will be released and the output stage re-enabled as the current entering the e/a falls approximately below 10 m a. +vo d97in591 - + 2 r1 r2 ccomp. e/a 1 2.5v d i - + x pwm driver 2.25v 40 m a d i figure 3. error amplifier and overvoltage detector block. v out nominal i sc 40 m a e/a output 2.25v dynamic ovp static ovp d97in592a over voltage 10 m a figure 4. dynamic and static ovp operation. AN966 application note 4/20
this dynamic ovp, with its combination of soft and sharp braking, is effective to handle most of load changes but does not provide a complete protection. in fact it is sensitive to output voltage variations (whence the appellative odynamico) and cannot reveal a steady overvoltage, which is likely to occur in case of load disconnection. the above mentioned concept of the e/a saturation is effective to achieve a ostatico ovp. if the overvol- tage lasts so long that the output of e/a goes below 2.25v (the e/a is in linear dynamics up to 2.5v), the protection is activated. besides turning off the output stage and the external mosfet, it disables some internal blocks reducing the quiescent current of the chip to 1.4ma (typ). the operation of the device is re-enabled as the e/a output goes back into its linear region. fig. 4 illustrates the combined action of dynamic and static ovp. zero current detection and triggering block (see fig. 5) the zero current detection (zcd) block switches on the external mosfet as the voltage across the boost inductor reverses, just after the current through the boost inductor has gone to zero. this feature allows tm operation. as the circuit is running, the signal for zcd is obtained with an auxiliary winding on the boost inductor. of course, a circuit is needed that turns on the external mosfet at start-up since no signal is coming from the zcd. this is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the mosfet, producing also the signal for arming the zcd circuit. the repetition rate of the starter is greater than 70 ms ( @ 14 khz) and this maximum frequency must be taken into account at design time. disable block (see fig. 5) the zcd pin is used also to activate the disable block. if the voltage on the pin is taken below 150 mv the device will be shut down. as a result, its current consumption will be reduced. to re-enable the de- vice operation, the pull-down on the pin must be released. multiplier block (see fig. 6) the multiplier has two inputs: the first one takes a partition of the instantaneousrectified line voltage and the second one the output of the e/a. if this voltage is constant (over a given line half-cycle) the output of the multiplier will be shaped as a rectified sinusoid too. this is the reference signal for the current comparator, which sets the mosfet peak current cycle by cycle. d97in674 1.1v 0.15v starter disable 5 gd driver + +- - 5.7v r s q +vi zcd pwm 7 200 m a figure 5. zero current detection, triggering and disable block. AN966 application note 5/20
current comparator and pwm latch (see fig.7): the current comparator senses the voltage across the current sense resistor (rs) and, by comparing it with the programming signal delivered by the multiplier, determines the exact time when the external mosfet is to be switched off. the pwm latch avoids spurious switchings of the mosfet which might result from the noise generated. the output of the multiplier is internally clamped to 1.7v, (typ.) thus current limiting occurs if the voltage across rs reaches this value. driver (see fig.8) a totem pole buffer, with 400ma source and sink capability, allows to drive an external mosfet. an in- ternal pull-down circuit holds the output low when the device is in uvlo conditions, to ensure that the external mosfet cannot be turned on accidentally. d97in676 + - r s 4 x q driver r s q cmp 1.7v figure 7. current comparator and pwm latch d97in675 + - e/a 4 x curr.cmp 23 rs 1.7v figure 6. multiplier block. AN966 application note 6/20
tm pfc operation (boost topology) the operation of the pfc transition mode controlled boost converter, can be summarized in the follow- ing description. the ac mains voltage is rectified by a diode bridge and the rectified voltage delivered to the boost con- verter. this, using a switching technique, boosts the rectified input voltage to a regulated dc output volt- age (vo). the boost converter consists of a boost inductor (l), a controlled power switch (q), a catch diode (d), an output capacitor (co) and, obviously, a control circuitry (see fig. 9). the goal is to shape the input current in a sinusoidal fashion, in-phase with the input sinusoidal voltage. to do this the l6561 uses the so-called transition mode technique. the error amplifier compares a partition of the output voltage of the boost converter with an internal ref- erence, generating a signal error proportional to the difference between them. if the bandwidth of the er- ror amplifier is narrow enough (say, below 20 hz), the error signal is a dc value over a given half-cycle. the error signal is fed into the multiplier block and multiplied by a partition of the rectified mains voltage. the result will be a rectified sinusoid whose peak amplitude depends on the mains peak voltage and the value of the error signal. the output of the multiplier is in turn fed into the (+) input of the current comparator, thus it represents a sinusoidal reference for pwm. in fact, as the voltage on the current sense pin (istantaneous inductor current times the sense resistor) equals the value on the (+) of the current comparator, the conduction of the external mosfet is terminated. as a consequence, the peak inductor current will be enveloped by a d97in677 7 6 8 gd uvlo gnd driver v cc q figure 8. output driver. l i l i q i d i o d d94in119 q controller c in i c c o load ~ ~ figure 9. boost converter circuit. AN966 application note 7/20
rectified sinusoid. it is possible to prove also that this operation produces a costant on-time over each line half-cycle. after the mosfet has been turned off, the boost inductor discharges its energy into the load until its current goes to zero. the boost inductor has now run out of energy, the drain node is floating and the inductor resonates with the total capacitance of the drain. the drain voltage drops rapidly below the in- stantaneous line voltage and the signal on zcd drives the mosfet on again and another conver- sion cycle starts. this low voltage across the external mosfet at turn-on reduces both the switching losses and the equivalent drain capacitance energy that is dissi- pated inside the external mosfet. the resulting inductor current and the timing inter- vals of the mosfet are shown in fig. 10, where it is also shown that, by geometric relationships, the av- erage input current (the one which will be drawn from the mains) is just one-half of the peak inductor current waveform. the system operates (not exactly on but very close to) the boundary between continuous and discon- tinuous current mode and that is why this system is called a transition mode pfc. besides the simplicity and the few external parts required, this system minimizes the inductor size due to the low inductance value needed. on the other hand, the high current ripple on the inductor involves high rms current and high noise on the rectified main bus, which needs a heavier emi filter to be re- jected. these drawbacks limit the use of the tm pfc to lower power range applications. design criteria here below some design criteria are described. the basic design specification concerns the following data: q mains voltage range: v irms(min) -v irms(max) q regulated dc output voltage: v o q rated output power: p o q minimum switching frequency: ? sw q maximum output voltage ripple: d v o q maximum overvoltage admitted: d v ovp for reference, it is useful to define also the following quantities: q expected efficiency: h q input power: pi (= p o / h ) q maximum mains rms current: i rms (= pi/v irms(min) ) q rated output current: io (= po/vo) power section design input bridge the input diodes bridge can use standard slow recovery, low-cost devices. the quantities to consider will be just the input current (i rms ), the maximum peak mains voltage and the thermal data of the diodes. input capacitor the input high frequency filter capacitor (c in ) has to attenuate the switching noise due to the high fre- d93in040a inductor current peak average mosfet q 0 off on figure 10. inductor current waveform and mosfet timing AN966 application note 8/20
quency inductor current ripple (twice the average line current, see fig. 9). the worst conditions will occur on the peak of the minimum rated input voltage. the maximum high frequency voltage ripple is usually imposed between 1% and 10% of the minimum rated input voltage. this is expressed by a coefficient r (r = 0.01 to 0.1): c in = i rms 2 p ?? sw ? r ? v irms ( min ) in real conditions the input capacitance will be designed taking the emi filter into account. output capacitor the output bulk capacitor (c o ) selection depends on the dc output voltage, the admitted overvoltage, the output power and the desired voltage ripple. the 100 to 120hz (twice the mains frequency) voltage ripple ( d v o = 1/2 ripple peak-to-peak value) is a function of the capacitor impedance and the peak capacitor current (i c(2f)pk =i o ): d v o = i o ? `````````` ` 1 ( 2 p ? 2f ? c o ) 2 + esr 2 with a low esr capacitor the capacitive reactance is dominant, therefore: c o i o 4 p ? f ? d v o = p o 4 p ? f ? v o ? d v o d vo is usually selected in the range of 1 to 5% of the output voltage. although esr usually does not affect the output ripple, it has to be taken into account for power losses calculation. the total rms capacitor ripple current, including mains frequency and switching frequency components, is: i crms = ```````````` ` 32 `` 2 9 p ? i rms 2 ? v irms v o - i o 2 if the application has to guarantee a specified hold-up time, the selection criterion of the capacitance will change: co has to deliver the output power for a certain time (t hold ) with a specified maximum dropout voltage: c o = 2 ? p o ? t hold v o_min 2 - v op_min 2 where vo_min is the minimum output voltage value (which takes load regulation and output ripple into account) and vop_min is the minimum output operating voltage before the 'power fail' detection from the downstream system supplied by the pfc. boost inductor designing the boost inductor involves several parameters and different approaches can be used. first, the inductance value must be defined. the inductance (l) is usually determined so that the mini- mum switching frequency is greater than the maximum frequency of the internal starter, to ensure a cor- rect tm operation. assuming unity pf, it is possible to write: ton = l ? i lpk ? sin (q) ` ` 2 ? v irms ? sin (q) = l ? i lpk `` 2 ? v irms toff = l ? i lpk ? sin (q) vo - `` 2 ? v irms ? sin (q) being ton and toff the on-time and the off-time of the power mosfet respectively, i lpk the maxi- AN966 application note 9/20
mum peak inductor current in a line cycle and q the instantaneous line phase ( q (0, p )). note that the on-time is constant over a line cycle. as previously said, i lpk is twice the line-frequency peak current, which is related to the input power and the line voltage: i lpk =2 ? ` ` 2 ? p i v irms . substituting this relationship in the expressions of ton and toff, after some algebra it is possible to find the instantaneousswitching frequency along a line cycle: f sw (q) = 1 ton + toff = 1 2 ? l ? p i ? v 2 irms ? ( v o - ` ` 2 ? v irms ? sin (q)) v o . the switching frequency will be minimum at the top of the sinusoid ( q = p /2 ? sin( q ) =1 ), maximum at the zero crossings of the line voltage ( q =0or p ? sin( q ) = 0) where toff = 0. the absolute minimum frequency ? sw(min) can occur at either the maximum or the minimum mains volt- age, thus the inductor value is defined by: l = v 2 irms ? ( v o - ` ` 2 ? v irms ) 2 ?? sw ( min ) ? p i ? v o , where v irms can be either v irms(min) or v irms(max) , whichever gives the lower value for l. the minimum suggested value for ? sw(min) is 15 khz, not to interfere with the internal starter (see zcd and triggering block description) . once defined the value of l, the real design of the inductor can start. as to the magnetic material and the geometry, the need of isolation due to the high voltage, and the operating frequency range make the standard high frequency ferrite (gapped core-set with bobbin) the usual choice in pfc applications. among the various types offered by manufacturers the most suitable one will be selected with technical and economic considerations. the next step is to estimate the core size. to get the approximated value of the minimum core size, it is possible to use the following practical formula: volume 4 ? l ? i rms 2 , where volume is expressed in cm 3 and l in mh. then the winding must be specified. the turn number and the wire cross-section are the quantities to be defined. the (maximum) instantaneous energy inside the boost inductor (1/2 ? l ? i lpk 2 ) can be expressed in terms of energy stored in the magnetic field, given by the maximum energy density times the effective core volume v e : 1 2 ? l ? i lpk 2 = 1 2 ? d h ? d b ? v e 1 2 ? d h ? d b ? a e ? i e , where: a e is the effective area of the core section, l e is the effective magnetic path length (both data are taken from the data sheet of the core set), d h is the swing of the magnetic field strength and d bisthe swing of the magnetic flux density. to prevent the core from saturating because of its high permeability and allow an adequate d h, it is nec- essary to introduce an air gap. despite the gap length l gap is few per cent of l e , the permeability of ferrite is so high (for power ferrites, typically m r = 2500) that it is possible to assume all the magnetic field concentrated in the air gap with good approximation ( d h d h gap ). for instance, with 1% of l gap /l e (which is the minimum suggested value) the er- ror caused by this assumption is about 4%. the error will be smaller if the l gap /l e ratio is larger. AN966 application note 10/20
as a result, neglecting fringing flux in the air gap region, the energy balance can be re-written as: l ? i lpk 2 d h gap ? d b ? a e ? i gap the flux density d b is the same throughout the core and the air gap and is related to the field strength inside the air gap by the well-known relationship: d b =m 0 ? d h gap . then, considering ampere's law (applied to the air gap region only): i gap ? d h gap n ? i lpk , from the energy balance equation it is possible to obtain: l m 0 ? n 2 ? a e i gap ? n ```` l ? l gap m o ? a e , where n is the turn number of the winding. as n is defined, it is recommended to check for the saturation of the core (see pin 4 description). if the check shows a result too close to the rated limit, an increase of l gap and a new calculation will be neces- sary. the wire gauge selection is based on limiting the copper losses at an acceptable value: p cu = 4 3 ? i rms 2 ? r cu ; due to the high frequency ripple the effective wire resistance r cu is increased by skin and proximity ef- fects. for this reason litz wire or multi-wire solutions are recommended. finally, the space occupied by the winding will be evaluated and, if it does not fit the winding area of the bobbin, a bigger core set will be considered and the winding calculation repeated. it is now necessary to add an auxiliary winding to the inductor, in order for the zcd pin to recognize when the current through the inductor has gone to zero. it is anyway a low cost thin wire winding and the turns number is the only parameter to be defined (see pin 5 description). power mosfet the choice of the mosfet concerns mainly its r dson , which depends on the output power, since the breakdown voltage is fixed just by the output voltage, plus the overvoltage admitted and a safety margin. the mosfet's power dissipation depends on conduction and switching losses. the conduction losses are given by: p on = i qrms 2 ? r dson where: i qrms = 2 ? `` 2 ? i rms ? ```````` ` 1 6 - 4 `` 2 9 p ? v irms v o . the switching losses due to current-voltage cross occur only at turn-off because of the tm operation: p cross = v o ? i rms ? t fall ?? sw , AN966 application note 11/20
where t fall is the crossover time at turn-off. at turn-on the loss is due to the discharge of the total drain capacitance inside the mosfet itself. in general, these losses are given by: p cap = ? ? ? 3.3 ? c oss ? v drain 1.5 + 1 2 ? c d ? v drain 2 ? ? ? ?? sw , where c oss is the internal drain capacitance of the mosfet (@ v ds = 25v), cd is the total external drain parasitic capacitance and v drain is the drain voltage at mosfet turn-on. in practice it is possible to give only a rough estimate of the total switching losses because both ? sw and v drain change along a given line half-cycle. v drain , in particular, is affected not only by the sinusoidal change of the input volt- age but also by the drop due to the resonance of the boost inductor with the total drain capacitance (see fig. 12). this causes, at low mains voltage, v drain to be zero during a significant portion of each line half-cycle. boost diode the boost freewheeling diode will be a fast recovery one. the value of its dc and rms current, useful for losses computation, are respectively: i do =i o i drms = 2 ? ` ` 2 ? i rms ? `````` ` 4 ` ` 2 9 p ? v irms v o . the conduction losses can be estimated as follows: p don = v to ? i do + r d ? i drms 2 , where v to (threshold voltage) and r d (differential resistance) are parameters of the diode. the breakdown voltage is fixed with the same criterion as the mosfet. l6561 biasing circuitry (pin by pin) please, refer to the schematic circuit shown in fig. 13. pin 1 (inv) leads both to the inverting input of the e/a and to the ovp circuit. a resistive divider will be connected between the regulated output voltage of the boost and the pin. the internal reference on the non-inverting input of the e/a is 2.5v and the ovp alarm level current is 40 m a. r7 and r8 will be then selected as follow: r7 r8 = v o 2.5v - 1r7 = d v ovp 40 m a , pin 2 (comp) is the output of the e/a and also one of the two inputs of the multiplier. a feedback com- pensation network, placed between this pin and inv (1), reduces the bandwidth so to avoid the attempt of the system to control the output voltage ripple (100-120hz). in the simplest case, this compensation is just a capacitor, which provides a low frequency pole as well as a high dc gain. a simple criterion to define the capacitance value, is to set the bandwidth (bw) from 20 to 30hz: bw = 1 2 p ? ( r7 / / r8 ) ? c3 c3 = 1 2 p ? ( r7//r8 ) ? bw AN966 application note 12/20
please refer to [1] for more information on how to compensate the e/a. pin 3 (mult) is the second multiplier input. it will be connected, through a resistive divider, to the rec- tified mains to get a sinusoidal voltage reference. the multiplier can be described by the relationship: v cs = k ? ( v comp - 2.5v ) ? v mult where v cs (multiplier output) is the reference for the current sense, k is the multiplier gain, v comp is the voltage on pin 2 (e/a output) and v mult is the volt- age on pin 3. a complete description is given by the diagram of fig. 11, which shows the typical multiplier charac- teristics family. the linear operation of the multiplier is guaranteed inside the range 0 to 3v of v mult and the range 0 to 1.6v of v cs , while the minimum guaranteed value of the maximum slope of the characteristics family ( d v cs / d v comp ) is 1.65. tak- ing this into account, the following is the suggested procedure to set properly the operating point of the multiplier. first, the maximum peak value for v mult ,v multpkx , is selected. this value, which will occur at maximum mains voltage, should be 3v or nearly so in wide range mains and less in case of single mains. the minimum peak value, occurring at minimum mains voltage will be: v multpkmin = v multpkx ? v irms ( min ) v irms ( max ) this value, multiplied by the minimum guaranteed d v cs d v comp will give the maximum peak output voltage of the multiplier: v xcspk = 1.65 ? v multpkmin if the resulting v xcspk exceeds the linearity limit of the current sense (1.6v), the calculation should be re- peated beginning with a lower v multpkx value. in this way, the divider will be such that: r10 r9 + r10 = v multpkx ` ` 2 ? v irms ( max ) the individual values can be chosen by setting the current through r10, in the hundreds m a or less to minimise power dissipation. pin 4 (cs) is the inverting input of the current sense comparator. through this pin, the l6561 reads the in- stantaneousinductor current, converted to a proportional voltage by an external sense resistor (rs). as this signal crosses the threshold set by the multiplier output, the pwm latch is reset and the power mosfet is turned off. the mosfet will stay in off-state until the pwm latch is set again by the zcd signal. an inter- nal circuit ensures that the pwm latch cannot be set until the signal on pin 4 has disappeared. the sense resistor value is calculated as follows: r s v xcspk i rspk v mult (pin3) (v) d97in555a 2.6 3.0 3.2 3.5 4.5 5.0 v comp (pin2) (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v cs (pin4) (v) 4.0 2.8 upper voltage clamp figure 11. multiplier characteristics family AN966 application note 13/20
where v xcspk has been calculated as per described earlier and: i rspk =2 `` 2 ? i rms , the power dissipated in rs, given by: p rs = 4 3 ? r s ? i rms 2 , will not exceed 1% of the rated output power. the internal 1.8v (max.) zener clamp on the non-inverting input of the pwm comparator sets a current limitation threshold, so that the maximum current through rs is: i rspkmax = 1.8 r s . this will be the maximum inductor current as well, therefore this value has to be used when checking for the ferrite core saturation. pin 5 pin 5 (zcd) is the input to the zero current detector circuit. the zcd pin will be connected to the auxiliary winding of the boost inductor through a limiting resistor. the zcd circuit is negative-going edge-triggered: when the voltage on the pin falls below 1.6 v the pwm latch is set and the mosfet is turned on. to do so, however, the circuit must be armed first: prior to falling below 1.6v the voltage on pin 5 must experience a positive-going edge exceeding 2.1 v (due to mosfet's turn-off). the maximum main-to-auxiliary winding turn ratio, m, has to ensure that the voltage delivered to the pin during mosfet's off-time is sufficient to arm the zcd circuit. then: m v o - ` ` 2 ? v irms ( max. ) 2.1 if the winding is used also for supplying the ic, the above criterion may not be compatible with the vcc voltage range. to solve this incompatibility the self-supply network shown in the schematic of fig. 13 can be used. the minimum value of the limiting resistor can be found assuming 3 ma current through the pin and considering the maximum voltage (the ab- solute value) across the auxiliary winding. the actual value can be then fine-tuned trying to make the turn-on of the mosfet occur exactly on the valley of the drain voltage oscillation (the boost inductor, completely discharged, is ringing with the drain capacitance, see fig. 12). this will minimize the power dissipation at turn-on. if the pin is driven by an external signal, the l6561 will be synchronized to (the negative-go- ing edges of) that signal. if left floating, the l6561 will work at the frequency of its internal starter. obviously, neither tm operation will take place nor high pf will be achieved in this case, but these characteristics can be exploited in ap- plications other than pfc. this pin incorporates also a disable function. the device will be shut down if the voltage on the pin is forced externally below 150mv. to do so, up to 10ma must be sunk from the pin. the quiescent current of the ic will be reduced at about 1.4 ma. the device will restart as the ex- ternal pull-down is removed since an internal 150 m a generator pulls up the pin. 0.7 t d97in678a t 5.7 v zcd v ipk v o v drain 1.6 2.1 figure 12. optimum mosfet turn-on AN966 application note 14/20
pin 6 (gnd). this pin acts as the current return both for the signal internal circuitry and for the gate drive current. when layouting the printed circuit board, these two paths should run separately. pin 7 (gd) is the output of the driver. the pin is able to drive an external mosfet with 400ma source and sink capability. to avoid undesired switch-on of the external mosfet because of some leakage current when the sup- ply of the chip is below the uvlo threshold, an internal pull-down circuit holds the pin low. the circuit guarantees 0.3v maximum on the pin (@ i sink = 10ma), with v cc > 3v. this allows to omit the obleedero resistor connected between the gate and the source of the external mosfet used to this purpose. pin 8 (v cc ) is the supply of the device. this pin will be externally connected to the start-up circuit (usu- ally, one resistor connected to the rectified mains) and to the self-supply circuit. whatever the configuration of the self-supply system, a capacitor will be connected between this pin and ground. to start the l6561, the voltage must exceed the start-up threshold (13v max.). below this value the de- vice does not work and consumes less than 90 m a from v cc . this allows the use of high value start-up re- sistors (in the hundreds k w ), which reduces power consumption and optimises system efficiency at low load, especially in wide range mains applications. when operating, the current consumption (of the device only, not considering the gate drive current) rises to a value depending on the operating conditions but never exceeding 4.5ma. the device keeps on working as long as the supply voltage is over the uvlo threshold (10.3v max). if the vcc voltage exceeds 18v an internal zener diode, 30 ma rated, will be activated in order to clamp the voltage. in that case the power consumption of the device will increase considerably. practical design example to fix the main concepts, here below the wide range demonstration board design is described and the results of the board evaluation are presented. the target specifications are summarised in table1. to meet them an appropriate selection, especially as to critical components, is an important step. table 1. wide range pfc target specification. ac mains rms voltage v irms = 85 to 265v dc output regulated voltage v o = 400v rated output power p o = 80w minimum switching frequency f sw(min) > 20khz expected efficiency h > 90% full load output voltage ripple d v o 10v maximum output overvoltage d v ovp = 40v power mosfet: two parameters are useful to select the suitable device: the minimum blocking voltage v (br)dss and the r dson because of power dissipation. the device selected is the stp8na50 (v (br)dss = 500v, r dson = 0.85 w @25 c, 1.5 w @ 100 c). the estimated power dissipations are 1.3 w for conduction, and 0.2 w total switching losses (crossover + ca- pacitive). boost diode (d1): fast recovery diode suitable for rated breakdown voltage are used on demoboards. the plastic axial package byt13-600 has been selected. the power dissipation is about 0.2w. AN966 application note 15/20
boost inductor (t): the inductance value (l) is as high as 0.8 mh, which leads to a minimum switching frequency of 40khz. the minimum core size estimate gives a minimum volume of 3.3 cm 3 . considering the etd series, the etd29x16x10 core (5.4 cm 3 effective volume) is to be selected. to reduce copper losses, a multiple wire (10 x 0.2mm) has been adopted. the resistance of the winding is about 1 w at 40 khz , so the maximum copper losses are about 1.1 w. output filter capacitor (c5): the specification on the output voltage ripple determines the capacitance value. assuming 50 hz minimum line frequency, a 47 m f/450v capacitor has been selected. this gives an out- put ripple d vo = 7v. multiplier setting (r9 and r10) and sense resistor (r6): the multiplier divider is selected so to exploit all its linear dynamics (v multpkx = 3v) as per the procedure described in pin 3 description. the sense resistor is then determined. as to r6, metallic film resistors are suitable because of the high peak current flowing in it. output divider (r7 and r8): r7 is selected so to achieve the desired overvoltage trip level ( d v ovp = 40v), while r8 is chosen so to get the specified output regulated voltage. the schematic circuit of fig. 13 shows the values of all the parts used. in fig. 14 the printed circuit board and the component layout of the demonstration board are shown. table 2. demonstration board evaluation results. v in (vac) pin (w) v o (vdc) d v o (vdc) p o (w) h (%) pf thd (%) 85 89.8 399.7 14 82.5 91.9 0.999 4.9 110 88.4 399.8 14 82.6 93.4 0.998 5.9 135 87.4 399.8 14 82.6 94.5 0.995 6.8 175 87.1 399.8 14 82.6 94.8 0.988 7.9 220 86.8 399.8 14 82.6 95.1 0.977 8.8 265 86.6 399.8 14 82.6 95.3 0.972 9.8 8 3 bridge 4 x 1n4007 r9 (*) 1.24m c1 1 m f 400v r10 10k c2 22 m f 25v fuse 4a/250v vac (85v to 265v) r3 (*) 240k d3 1n4150 d2 1n5248b r2 100 12nf c6 r1 t 5 6 l6561 7 21 c3 1 m f r5 mos stp8na50 d1 byt13-600 r7 (*) 998k c5 47 m f 450v vo=400v po=80w + - d97in553b transformer t: core thomson-csf b1et2910a (etd 29 x 16 x 10mm) or equivalent (orega 473201a8) primary 90t of litz wire 10 x 0.2mm secondary 7t of #27 awg (0.15mm) gap 1.25mm for a total primary inductance of 0.8mh r6 (*) 0.41 1w r8 6.34k 1% + - c7 10nf ntc (*) r3 = 2 x 120k w r6 = 0.82 w /2 r7 = 2 x 499k w , 1% r9 = 2 x 620k w 4 68k 10 figure 13. wide range demonstration board electrical circuit. AN966 application note 16/20
demo board evaluation results to evaluate the performance of the pfc demonstration board, the following parameters have been measured: pf(power factor), thd%(current total harmonic distortion), d vo (peak-to-peak output voltage ripple), vo (output voltage), h (efficiency). the test equipment set-up is shown in fig. 15 and the results are shown in table 2. the harmonic content measurement has been done with an emi/rfi filter interposed between the ac source and the demo board under test, while the efficiency has been calculated without the filter contri- bution. the filter is configured as shown in fig. 16, where: t1 = 1mh, t2 = 27mh, cx = 0.47 m f / 630v, cy = 2.2nf / 630v figure 14. p.c. board and components layout of the fig. 13 (1:1.25 scale) c o m p o n e n t s s i d e s o l d e r s i d e AN966 application note 17/20
application ideas the l6561 is a versatile device. besides the typical application as a pfc preregulator based on boost topology, it fits also other applications and/or topologies. some application hints are given in the follow- ing. ac power source/analyzer hp6813a emi filter d97in679 l6561 pfc demo resistive load figure 15. test equipment set-up c x d97in680 t1 t2 c y line pfc earth figure 16. emi filter configuration 2 1 l6561 4 7 3 5 6 8 85to 265 vac 24 vdc / 2a 680nf 1.5 m w 1.5 m w 220 k w 220 k w p6ke160p 1n4937 22 m f 39 k w 10 w 0.33 w 1/2 w 100 k w 2.4 k w 20k w 3.3k w 20 k w 22 k w 47 k w 4.7 k w tl431 4n35 4n35 220pf 1 m f stp7na60 byw80-150 1nf 1n4148 2a fuse 4.7 nf 2200 m f 25v 2200 m f 25v transformer spec: core: etd29, 3c85 grade pri: 2 paralleled windings, 71 t/awg27 each sec: 17 t, 5xawg27 sandwiched aux: 10t, awg32 evenly spaced lgap: 1mm for 620 m h primary inductance figure 17. wide range 50w pfc, flyback topology. AN966 application note 18/20
8 3 bridge 4 x by255 r9 1.8m 5% c1 0.22 m f 630v r10 6.2k 5% c2 22 m f 25v fuse vac r1 68k 5% t 5 6 l6561 7 21 c3 330nf r5 10 mos stp5n80 r4 330 4 d1 byt13-800 r2 1.3m 1% vo=320v po=140w + - d97in681 transformer t: core thomson-csf b1et2910a primary 150t of litz wire 10 x 0.2mm secondary 7t of #32 awg (0.15mm) primary inductance: 3mh r6 0.47 1w r8 12k 1% c4 1nf + - c6 10nf 277v +10% -15% v cc r12 330k r11 62k 1% c5 82 m f/100 m f 385v 3 2 4 v cc r3 12k 1% 8 lm358 a r7 1.3m 1% + - figure 19. vmains=277 vac, vo=320v, po=140w buck-boost topology 176 to 265 vac t1 l6561 fuse c2 10nf r1 750k r1a 750k r2 8.2k c3 680nf l6569 r8 9.53k r7a 750k r7 750k r6 1 d1 byt11600 r11 22 r31 1.5m r4 10 r12 2.2m r29 .6k r3 68k r14 dz1 4.7v d2 1n4148 d3 1n4148 dz2 18v d4 1n4148 dz3 5.6v dz4 20v d5 1n4148 r16 10 r18 10k r20 180k r10 56k r26 2.2m r28 56k r30 2.2m r27 220 r25 82k r22 1.5m r24 1.5m r21 820k r23 820k r19 330k r15 10 r17 10k r9 220k 1w r13 47 c8 10 m f c6 10 m f c10 470nf c13 470pf c14 560pf c17 6.8nf 630v c18 1 m f c16 6.8nf 630v c12 820pf 600v c5 22 m f 450v ntc bridge q4 s170 lp2 lp1 l2 2.3mh l1 2.3mh 100 16k c11 100nf stp6nb50 q2 stp6nb50 q3 c15 100nf 250v c15a 100nf 250v p0102aa scr c1 220nf 400v stp5na50 q1 c9 100nf 1 2 5 3 6 4 8 7 1 4 23 5 6 7 8 d97in682 figure 18. power factor corrected lamp ballast using the l6569 driver. reference: [1] ocontrol loop modelling of l6561-based tm pfco (an1089). AN966 application note 19/20
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia-brazil-canada-china-finland-france-germany- hong kong-india-israel-italy-japan-m alaysia-malta-morocco-singapore- spain- sweden-switzerland-united kingdom-united states. http://www.st.com AN966 application note 20/20

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